1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, and in particular to a semiconductor integrated circuit device which generates and distributes a synchronous clock signal.
2. Description of the Related Art
In LSI for microprocessors using a CMOS circuit, a clock signal is distributed to an internal CMOS circuit, and operations are performed according to the timing of the clock signal. In general, a phase-locked loop (PLL) is built into the LSI as a circuit for generating the clock signal. The clock signal is generated by a crystal oscillator circuit, etc., outside the LSI. The signal is then input to the LSI, the PLL performs frequency multiplication and phase synchronization, and the clock signal is distributed to the LSI internal circuit.
One example of a microprocessor using a PLL is the system described in “Hitachi SuperH RISC engine SH7750 Hardware Manual” pp. 10-15, published in April 1998. A block diagram of this prior art example is shown in FIG. 28. The clock signal generated by the crystal oscillator circuit is input from terminals xtal and extal of an oscillator OSC, divided by a frequency divider D1V1, and transmitted to a PLL PLL1. In the PLL PLL1, the frequency of the input clock signal is multiplied by a factor of, e.g., 6 times, and is output. This multiplied clock signal is shaped into clock signals of desired frequencies through a frequency divider DIV2, and is distributed to the LSI internal circuit as plural clock signals. These clock signals are further supplied to a PLL PLL2, phase-synchronized, and output to the exterior of the LSI from a terminal ckio.
A prior art example of a PLL is shown in FIG. 26. An input clock signal clkin and output clock signal clkout which have been divided by a frequency divider DIV00 are input to a phase frequency detector PFD, and their frequency difference and phase difference are detected. The detected frequency difference and phase difference are converted into a control voltage by a charge pump CP and low pass filter circuit LPF, and are used as a control signal of a voltage control oscillator circuit VCO. The voltage control oscillator circuit VCO outputs a clock signal as the output clock signal clkout according to the control voltage, and feeds it back to the phase frequency detector PFD through the frequency divider DIV00. By repeating this process, the PLL generates the output clock signal clkout which is phase-synchronized with the input clock signal clkin and having a multiplied frequency. The time until the clock signal output by the PLL can be supplied stably with the desired phase and frequency is referred to as the clock settling time. For example, in the example described on pp. 346 to 347 of the 1999 IEEE International Solid-State Circuits Conference Digest of Technical Papers (February 1999), the clock settling time of the PLL is 40 periods of the clock signal.
In CMOS LSI used in microprocessors for portable devices in recent years, attempts are being made to reduce power consumption by such means as suspending supply of the clock signal to the circuit when the LSI internal circuit is not operating. Such an LSI has three kinds of states. One is an active state which performs normal operation. The second state is a sleep state where only the clock generating circuit is operating, the internal circuit is halted and the clock is not supplied to the internal circuit. The third state is a standby state where all circuits in the LSI are halted. In the standby state, the clock generating circuit is also stopped, and when the state changes from standby to active, the internal circuit cannot start operating and a fast return to the active state cannot be performed until the clock signal generated by the clock generating circuit stabilizes, i.e., during the clock stability period. Hence, in the sleep state, only the internal circuit is stopped and the clock generating circuit is made to function. When there is a state change from the sleep state to the active state, as the clock signal can be supplied stably, there is a fast return to the active state. However, the power consumption is larger than in the standby state due to operation of the clock generating circuit. The reason why a fast return to the active state from the standby state is not possible, is that the clock settling time of the PLL which is the clock generating circuit, is 40 periods of the clock signal, as described on p. 346 to p. 347 of the 1999 IEEE International Solid-State Circuit Conference Digest of Technical Papers (February 1999). If a clock generating circuit having a short clock settling time of 2-3 periods can be used for the clock generating circuit in a microprocessor, a fast return to the active state would be possible even if operation of the clock generating circuit stops in the sleep state.